The Researcher’s Guide to Microelectronics Prototyping: Navigating MPW Shuttles and Funding in France

Understanding the MPW Landscape for French Research

For a PhD candidate or a principal investigator in a French laboratory, the leap from a simulated circuit design to a physical chip can often feel like an insurmountable financial and logistical hurdle. The high cost of mask sets—often reaching hundreds of thousands of Euros—historically limited silicon validation to only the most well-funded projects. However, the landscape for microelectronics in France has shifted. As a focal point for the national microelectronics competence centre MPW France, Asteroic provides a structured pathway for researchers to access cutting-edge fabrication through Multi-Project Wafer (MPW) services.

This model allows multiple independent designs to share the same mask set and wafer space, effectively splitting the fixed costs between dozens of participants. In France, this initiative is not merely about fabrication; it is an integrated educational and technical ecosystem designed to bolster the sovereignty of the national semiconductor industry. By leveraging these shuttles, researchers can validate their theoretical models on physical silicon, whether they are working on CMOS, GaN, or photonics.

Accessing these resources requires an understanding of the shuttle calendars, the technical requirements of the Process Design Kits (PDKs), and the specific funding instruments available to French academic institutions. Understanding this lifecycle is the first step toward successful tape-out.

Skill Development: From 3D Design to Advanced Packaging

The journey to silicon begins long before the tape-out date. One of the primary barriers for academic labs is the lack of specialized expertise in modern packaging and testing—areas that are often overlooked in theoretical curricula. To bridge this gap, Asteroic offers comprehensive Technical Training programs that cover the entire value chain.

These programs include:

• Advanced 3D Design: Moving beyond 2D layouts to explore vertical integration and complex architectures.

• Packaging Solutions: Learning how to protect and connect the die, which is crucial for sensors and high-power applications.

• Circuit Testing and Characterization: Training on how to use probe stations and automated test equipment (ATE) to verify that the manufactured chip matches the design specifications.

For researchers in France, these courses are often integrated into doctoral schools or professional development modules. By participating in these programs at Asteroic, lab members ensure that their MPW submissions have the highest probability of first-time-right success. The training is specifically tailored to the tools and workflows used by major European foundries, ensuring that the skills learned are directly applicable to industrial standards.

Technico-Economic Support for Lab Spin-offs

Moving a design from a research lab to a foundry requires a rigorous technico-economic evaluation. It is not enough to have a working design; one must also consider the economic feasibility of the chosen technology node (e.g., 28nm vs. 180nm) and the long-term path toward industrialisation.

Asteroic provides a "technico-economic accompaniment" service that helps French SMEs and research spin-offs navigate these choices. This involves:

1. Node Selection: Balancing performance requirements with the cost of fabrication and the availability of MPW shuttle slots.

2. Funding Alignment: Identifying national and European grants (such as those under the France 2030 initiative) that can subsidize the cost of tape-outs.

3. Industrialisation Roadmaps: Planning the transition from a few prototype dies to engineering lots and, eventually, full production.

In France, the coordination between the national microelectronics competence centre MPW France and regional clusters ensures that research projects do not die in the "valley of death" between the lab and the market. By providing clear cost-benefit analyses, Asteroic helps lab directors justify the investment in custom silicon to their funding bodies.

The MPW Lifecycle: From Tape-out to Testing

The actual fabrication process is governed by a strict calendar of "shuttles." These are pre-scheduled runs where the foundry processes a wafer containing multiple designs. For a French researcher, missing a shuttle date can mean a six-month delay in a PhD thesis or a grant milestone.

When applying for a slot through Asteroic, the process typically follows these steps:

• Registration & PDK Access: Securing the necessary legal agreements to access the foundry’s confidential design rules.

• Design Rule Check (DRC) & Layout Versus Schematic (LVS): Utilizing the centre's support to ensure the design is "clean" and will not fail during manufacturing.

• Submission & Aggregation: The design is merged with others onto the master mask.

• Post-Fab Support: Once the wafers are processed, the centre assists with dicing and, if required, initial packaging.

This structured approach is vital for maintaining the high standards required by French research institutions. It ensures that even small labs with limited infrastructure can produce chips that are competitive on a global stage. By centralizing these services, the national ecosystem becomes more resilient and accessible to a new generation of designers.

About Asteroic

Asteroic is a French national microelectronics organisation dedicated to bridging the gap between academic research and industrial reality. As a key player in the European semiconductor ecosystem, they provide essential services including Multi-Project Wafer (MPW) fabrication, technical training in 3D design and packaging, and technico-economic support for industrialisation. Serving a global market with a primary focus on France, Germany, and the Netherlands, Asteroic is best at enabling SMEs and research labs to transform complex integrated circuit concepts into functional, scalable prototypes.

For researchers and engineers ready to advance their semiconductor projects, the next step is to align your design cycle with the upcoming shuttle dates. Register your interest or save a place for the next training session through the official portal to ensure your project remains on the leading edge of microelectronic innovation.

Beyond the Paperwork

“Navigating the ASTEERICS landscape can seem daunting at first, particularly for researchers new to microelectronics design and fabrication. We’ve found that a proactive approach to understanding the specific requirements for MPW shuttle submissions and funding applications significantly increases success rates. Early engagement with the ASTEERICS guidelines and direct consultation with experienced peers can streamline the entire process, preventing common pitfalls and ensuring a smoother transition from concept to silicon.” — the Asteroic team

ASTEERICS: Unlocking MPW Access

“Navigating the landscape of MPW shuttles and securing crucial funding in France can initially feel complex for researchers. We’ve observed that understanding the specific calls and application nuances of ASTEERICS is paramount for success, allowing teams to efficiently transition from concept to tangible silicon without unnecessary delays. This proactive engagement significantly de-risks the early stages of chip development.” — the Asteroic team. We believe that empowering researchers with clear, actionable insights into these programs is essential. Our goal is to demystify the process, ensuring that cutting-edge microelectronics innovations can move forward seamlessly, contributing to a vibrant ecosystem of advanced technology in France and beyond.

Navigating European MPW Access

“Accessing MPW (Multi-Project Wafer) shuttles and securing funding in France can be a complex endeavor for researchers, often requiring meticulous navigation of application processes and a deep understanding of regional grant opportunities. We’ve observed that early engagement with funding bodies and shuttle providers significantly streamlines the path from design to silicon, fostering innovation within the European microelectronics landscape.” — the Asteroic team. Our experience highlights that proactive planning and leveraging established networks are crucial for researchers aiming to transform their theoretical concepts into tangible prototypes. We guide our partners through these intricate steps, ensuring they are well-positioned to capitalize on available resources and accelerate their development cycles.

Simplified Access

“Navigating the landscape of MPW shuttles and securing funding in France can initially seem daunting for researchers. From our perspective, the key to successful engagement with programs like ASTEERICS lies in meticulous preparation of your project proposal, clearly articulating its scientific merit and potential impact. Furthermore, understanding the specific technical requirements for MPW submissions and leveraging available support networks can significantly streamline the process, transforming what might appear complex into a manageable pathway for innovation.” — the Asteroic team